Abstract:

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The quest for smaller transistors centers on nanoscale technology, which drives major breakthroughs in semiconductors by enabling hundreds of circuits on a chip through Very Large Scale and Ultra-Large Scale Integrations. However, reducing device dimensions generate short channel effects, (SCEs) in MOSFETs, which negatively affect its performance. This study evaluates the influence of key geometrical parameters; gate oxide thickness, channel length, and channel width on short channel effects (SCEs) in nanoscale double-gate FinFETs. The critical SCEs examined include Drain-Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), and Threshold Voltage (Vth) roll-off. FinFETs designed from Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) were analyzed using the PADRE simulator. The Results reveal that reducing gate oxide thickness is essential for minimizing DIBL and SS, with GaAs-FinFET achieving the lowest DIBL (4.38 mV/V) and Si-FinFET demonstrating the lowest SS (80.54 mV/dec) at 2 nm thickness. GaSb-FinFET outperforms others in threshold voltage, with the lowest Vth (0.33 V) at 14 nm thickness. Moreover, an optimal channel length of 45 nm effectively mitigates DIBL and SS, where GaAs-FinFET records the lowest DIBL (1.52 mV/V) and Si-FinFET exhibits the lowest SS (77.26 mV/dec). GaSb-FinFET achieves the lowest threshold voltage at 20 nm channel length. Additionally, channel width significantly affects SCEs, with an optimal width of 10 nm reducing these effects. At this width, (10 nm), GaAs-FinFET records the lowest DIBL of 4.38 mV/V, Si-FinFET achieves the lowest SS of 90.88 mV/dec, and GaN-FinFET demonstrates the lowest Vth (0.36 V). These findings underscore the importance of optimizing geometrical parameters to enhance FinFET performance and mitigate short channel effects, paving the way for improved nanoscale device design.

Keyward(s): DIBL, FinFETs, Geometrical Parameters, GaAs, GaSb, SCEs

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