Abstract:

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Continuous downscaling of Complementary Metal Oxide Semiconductor (CMOS) technology has driven the development of advanced transistor architectures such as Fin Field-Effect Transistor (FinFET) and Nanowire Field-Effect Transistor (NWFET), designed to suppress short-channel effects (SCEs) and enhance current drive. However, at sub-20 nm technology nodes, temperature-induced performance degradation becomes increasingly critical. This paper presents a comparative evaluation of temperature effects on the electrical characteristics of Si-FinFET and Si-NWFET devices using the PADRE simulator. The parameters studied include Drain-Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Threshold Voltage (Vth), Transconductance (Gm), and On/Off current ratio (Ion/Ioff), analyzed for a temperature range of 250–500 K under identical structural and biasing conditions. Results show that Si-NWFET exhibits significantly improved electrostatic control, achieving 93.7% lower DIBL and 56.5% lower SS compared to Si-FinFET. Si-NWFET also demonstrates 300.7% higher Ion/Ioff, confirming superior switching and leakage performance. Conversely, Si-FinFET achieves ~94% higher transconductance and 79.17% lower Vth, indicating a much stronger current-driving capability and lower power consumption. These results highlight the performance trade-offs between both architectures and provide useful insight for optimizing device design in future nanoscale CMOS technologies.

Keyward(s): CMOS Technology, FinFET, Nanowire Field-Effect Transistor (NWFET), Short-Channel Effects (SCEs), Temperature Effects, Transconductance

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