Abstract:

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The relentless scaling of transistor technology into the nanometer regime has exacerbated short-channel effects (SCEs), which significantly degrade device performance. Silicon nanowire field-effect transistors (Si-NWFETs) have emerged as promising candidates to mitigate these challenges due to their superior electrostatic control. However, the specific influence of a key geometric parameter, the nanowire diameter on SCEs remains inadequately explored and demands a thorough investigation. This study employs numerical simulations using the MuGFET tool's PADRE simulator to systematically evaluate the effect of silicon nanowire diameter, varied from 2 nm to 12 nm, on key SCE metrics and performance parameters. The results demonstrate a strong positive correlation between diameter and detrimental SCEs: drain-induced barrier lowering (DIBL) increases from 0.50 mV/V to 15.22 mV/V, and the subthreshold swing (SS) degrades from 75.23 mV/dec to 91.08 mV/dec as the diameter expands. Conversely, the threshold voltage exhibits a roll-off, decreasing from 0.73 V to 0.48 V with increasing diameter. Furthermore, the drain current and transconductance show a significant linear enhancement, improving by over five times, which is advantageous for drive strength and analog performance. This work reveals a critical performance trade-off: smaller diameters (2 nm) are optimal for electrostatic integrity and minimizing SCEs, while larger diameters (12 nm) are essential for achieving high on-current, transconductance, and switching speed. These findings provide vital design insights for optimizing Si-NWFET performance for specific applications and guiding future technology scaling.

Keyward(s): Drain-Induced Barrier Lowering (DIBL), Electrostatic Control, Nanowire Diameter, Silicon Nanowire FET (Si-NWFET), Transconductance

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